Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of flash memory cells arranged in blocks. A typical flash memory cell includes a storage layer capable of holding charges and that is electrically insulated from source and drain regions contained in a substrate by a layer of thin oxide (tunneling oxide). Each of the memory cells can be electrically charged by injecting electrons through the tunneling oxide layer into the storage layer. The charges can be removed from the storage layer by tunneling the electrons to the substrate through the tunneling oxide layer during an erase operation. Thus, the data in a memory cell is determined by the presence or absence of charges in the storage layer.
FIG. 1 illustrates a conventional memory cell having an asymmetric source and drain configuration. The memory cell includes two gate spacers, which includes storage layers. On the drain side, a storage layer 8 is separated from substrate 2 and gate electrode 4 by a tunneling layer 6. A further oxide layer 10 may be formed on storage layer 8. The spacer on the source side has a same structure as on the drain side. A lightly doped source region 12 is formed on the source side, wherein no lightly doped drain region is formed on the drain side. The state of storage layer 8 determines the threshold voltage of the memory cell. If electrons are stored, the memory cell exhibits a low threshold voltage. Conversely, if there are no electrons stored, the memory cell exhibits a high threshold voltage. The state of the memory cell may be determined by applying a voltage on word-line (gate electrode 4), wherein the voltage is between the high threshold voltage and the low threshold voltage. If the memory cell conducts, it is known that storage layer 8 has electrons stored therein. Otherwise, storage layer 8 has no electrons stored.
Conventionally, to form a lightly doped source region only, a non self-aligned formation method is used. As is illustrated in FIG. 2, photoresist 16 is formed to cover the drain side when lightly doped source region 12 is implanted. This process works for large-scale integrated circuit formation technologies. However, with the scaling of integrated circuits, the alignment of edge 18 of photoresist 16 with gate electrode 4 becomes increasingly difficult. A misalignment may cause edge 18 of photoresist 16 to fall on the left or right side of gate electrode 4, and thus a circuit failure may occur.
Accordingly, what is needed in the art is an improved method for forming memory cells having an asymmetric source and drain configurations.